Clock offset compensator

ABSTRACT

A device communicates with a host and includes a transmitter, a receiver and a clock generator that generates a local clock frequency. A clock recovery circuit communicates with the receiver and recovers a host clock frequency from data received from the host by the receiver. A frequency offset circuit communicates with the clock recovery circuit and the clock generator and generates a frequency offset based on the clock frequency and the recovered host clock frequency. A frequency compensator compensates a frequency of the transmitter using the frequency offset. The host and the device may communicate using a serial ATA standard. Frequency compensation can be performed during spread spectrum operation.

FIELD OF THE INVENTION

[0001] The present invention relates to clock compensation, and moreparticularly to compensating a local clock of a device that receivesdata from a host for frequency offset when transmitting data from thedevice to the host.

BACKGROUND OF THE INVENTION

[0002] A host and a device typically transmit and receive data to andfrom each other. For example in a personal computer environment, a diskdrive controller (host) is often connected to a disk drive (device). Thehost is typically implemented using a relatively accurate host clockgenerator. The accuracy is often required to meet the specifications ofa host processor and/or other host components.

[0003] The host and the device may be connected using a Serial AdvancedTechnology Attachment (SATA) standard, although other protocols may beused. The SATA standard is a simplified packet switching network betweena host and a device. SATA typically employs balanced voltage(differential) amplifiers and two pairs of wires to connect transmittersand receivers of the host and the device in a manner similar to100BASE-TX Ethernet. The SATA standard is disclosed in “Serial ATA: HighSpeed Serialized AT Attachment”, Serial ATA Organization, Revision 1.0,Aug. 29, 2001, and its Supplements and Errata, which are herebyincorporated by reference.

[0004] To reduce costs, the device may be implemented using a lessaccurate clock. For example, the device may include a resonator, whichmay be crystal or ceramic based. The resonator generates a referenceclock for a frequency synthesizer of a phase-locked loop (PLL), whichgenerates a higher-frequency clock. Ceramic resonators are cheaper thancrystal resonators but not as accurate. The resonator can be anindividual component. Alternately, the resonator can be implementedinside a clock chip (such as crystal voltage controlled oscillator(VCO)).

[0005] When the device is implemented using lower accuracy clockgenerators, the transmitted data from the device to the host may notmeet data transmission standards, such as SATA or other standards. As aresult, the device must be implemented with a more expensive local clockgenerator with improved accuracy, which increases the cost of thedevice.

SUMMARY OF THE INVENTION

[0006] A device according to the present invention communicates with ahost and includes a transmitter, a receiver and a clock generator thatgenerates a local clock frequency. A clock recovery circuit communicateswith the receiver and recovers a host clock frequency from data receivedfrom the host by the receiver. A frequency offset circuit communicateswith the clock recovery circuit and the clock generator and generates afrequency offset based on the clock frequency and the recovered hostclock frequency. A frequency compensator compensates a frequency of thetransmitter using the frequency offset.

[0007] In other features, the frequency compensator includes a low passfilter that communicates with the frequency offset circuit. Thefrequency compensator includes an accumulator that communicates with thelow pass filter and that generates a phase offset. The frequencycompensator includes an interpolator that receives a local phase fromthe clock generator and the phase offset from the accumulator. Theinterpolator outputs a compensated clock signal to the transmitter.

[0008] In yet other features, the clock generator includes aphase-locked loop circuit that includes a reference frequency generator,a phase detector that communicates with the reference frequencygenerator, a low pass filter that communicates with the phase detector,and a voltage controlled oscillator that communicates with the low passfilter. The reference frequency generator includes at least one of acrystal resonator and a ceramic resonator.

[0009] In still other features, a 1/N divider has an input thatcommunicates with the voltage controlled oscillator and an output thatcommunicates with the phase detector. A 1/M divider has an input thatcommunicates with the reference frequency generator and an output thatcommunicates with the phase detector. N and M are adjusted to create aspread spectrum modulation signal for spread spectrum operation. Aninterpolator communicates with an output of the voltage controlledoscillator and an input of the 1/N divider for smoothing.

[0010] In still other features, a summer has a first input thatcommunicates with an output of the low pass filter and an output thatcommunicates with an input of the accumulator. A frequency modulationgenerator communicates with a second input of the summer and selectivelygenerates a spread spectrum modulation signal when spread spectrumoperation is enabled and a constant signal when spread spectrumoperation is disabled.

[0011] In other features, the host and the device communicate using aserial ATA standard. The host can be a disk controller and the devicecan be a disk drive.

[0012] Further areas of applicability of the present invention willbecome apparent from the detailed description provided hereinafter. Itshould be understood that the detailed description and specificexamples, while indicating the preferred embodiment of the invention,are intended for purposes of illustration only and are not intended tolimit the scope of the invention.

BRIEF DESCRIPTION OF THE DRAWINGS

[0013] The present invention will become more fully understood from thedetailed description and the accompanying drawings, wherein:

[0014]FIG. 1 is a functional block diagram illustrating a host connectedto a device;

[0015]FIG. 2 is a functional block diagram illustrating a frequencyoffset compensator according to the present invention for a transmitterof the device of FIG. 1;

[0016]FIG. 3 is a more detailed functional block diagram of a firstembodiment of the frequency offset compensator for the transmitter ofthe device;

[0017]FIG. 4 is a functional block diagram of a second embodiment of afrequency offset compensator for the transmitter of the device and atriangular wave generator for optional spread spectrum operation;

[0018]FIG. 5 is an exemplary implementation of the frequency offsetcompensator of FIGS. 3 and 4;

[0019]FIG. 6 illustrates clock timing for an exemplary interpolatorshown in FIGS. 3-5;

[0020]FIG. 7 illustrates the host and the device of FIG. 1 with aconnection based on the SATA standard;

[0021]FIG. 8 illustrates a disk controller and a disk drive with aconnection based on the SATA standard;

[0022]FIGS. 9 and 10 illustrate phase-locked loop (PLL) circuitsaccording to the prior art; and

[0023]FIG. 11 illustrates a closed loop PLL for spread spectrumoperation according to the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0024] The following description of the preferred embodiment(s) ismerely exemplary in nature and is in no way intended to limit theinvention, its application, or uses. For purposes of clarity, the samereference numbers will be used in the drawings to identify similarelements.

[0025] Referring now to FIG. 1, a host 10 includes a receiver 12 and atransmitter 14. A device 20 includes a receiver 22 and a transmitter 24.The transmitter 14 of the host 10 transmits host data 26 to the receiver22 of the device 20. The transmitter 24 of the device 20 transmitsdevice data 28 to the receiver 12 of the host 10.

[0026] Referring now to FIG. 2, the device 20 includes a frequencyoffset compensator generally identified at 38. A local clock generator40 generates a local clock frequency f_(local). The device 20 alsoincludes a clock data recovery circuit 44 that determines a clockfrequency f_(data) of the host 10 from data transmitted by the host 10.A frequency offset calculator 48 compares the host frequency f_(data) tothe local frequency f_(local) and generates a frequency offsetf_(offset). The f_(offset) is used to compensate f_(local). For example,f_(offset) and f_(local) are summed by a summer 50. The compensatedfrequency is used to clock the transmitter 24 of the device 20. Bycompensating the frequency of the transmitter 24 of the device 20, aless expensive local clock generator can be used to reduce the cost ofthe device 20.

[0027] Referring now to FIG. 3, the host data 26 is received by thereceiver 22 of the device 20. A clock data recovery and frequency offsetcalculator 60 communicates with the receiver 22. A phase-locked loop(PLL) 64 generates a local phase p_(local), which is output to the clockdata recovery and frequency offset calculator 60. The clock datarecovery and frequency offset calculator 60 outputs a receiver clock tothe receiver 22 and a frequency offset f_(offset) to a low pass filter(LPF) 66, which has an output that is connected to an accumulator 68.

[0028] The accumulator 68 generates a phase offset p_(offset), which isinput to an interpolator 72. The interpolator 72 also receives p_(local)from the PLL 64. The interpolator 72 generates a compensated clocksignal based on p_(offset) and p_(local). An output of the interpolator72 communicates with the transmitter 24, which transmits the device data28.

[0029] Referring now to FIG. 4, an optional spread spectrum mode ofoperation may also be provided. A frequency modulator generator 84selectively generates a constant output and/or a spread spectrummodulation signal based upon a spread spectrum control signal (SSC). Forexample, the frequency modulation generator 84 can generate a triangularwave, a sine wave or any other spread spectrum modulation signal. Anoutput of the frequency modulation generator 84 is input to a firstinput of a summer 86. A second input of the summer 86 communicates withan output of the filter 66. An output of the summer 86 communicates withan input of the accumulator 68.

[0030] When the spread spectrum control (SSC) is enabled, the output ofthe filter 66 is summed with the spread spectrum modulation signal togenerate the phase offset p_(offset), which is input to the interpolator72. When spread spectrum control is disabled, the output of the filter66 is summed with a constant output of the frequency modulationgenerator 84 to generate the phase offset p_(offset), which is input tothe interpolator 72.

[0031] Referring now to FIG. 5, an exemplary implementation of thefrequency offset compensator 38 is shown. The device 20 employs a secondorder timing recovery circuit. The clock data recovery and frequencyoffset calculator 60 includes a clock data recovery circuit 100 havingan output connected to gain circuits 102 and 104. An output of the gaincircuit 102 (phase error) communicates with a first input of a summer106. An output of the gain circuit 104 (frequency error) communicateswith a first input of a summer 108.

[0032] An output of the summer 108 communicates with a delay element112, which has an output connected to a second input of the summer 106and a second input of the summer 108. The delay elements can beregisters. An output of the summer 106 is connected to an accumulator110 including a summer 114 and a delay element 118. The output of thesummer 114 is connected to a first input of the summer 114. An output ofthe summer 114 is connected to the delay element 118, which has anoutput connected to a second input of the summer 114 and to a firstinput of an interpolator 122.

[0033] In an exemplary implementation, the interpolator 122 operatesusing 128-phases at 375 MHz, although higher or lower phases and/orfrequencies can be used. A second input of the interpolator 122 isconnected to an output of the PLL 64. An output of the interpolator 122is input to the clock data recovery circuit 100. The clock data recoveryand frequency offset calculator 60 outputs the frequency offsetf_(offset), which is input to the LPF 66. An output of the LPF 66 isconnected to the summer 86.

[0034] An output of the frequency modulation generator 84 is connectedto a second input of the summer 86. An output of the summer 86 isconnected to a first input of a summer 152 in the accumulator 68. Anoutput of the summer 152 is connected to a delay element 156, which hasan output that is connected to the interpolator 72 and to a second inputof the summer 152. The interpolator 72 operates using 128-phases at 750MHz, although higher or lower phases and/or frequencies can be used.

[0035] Referring now to FIG. 6, operation of the interpolators isillustrated briefly. The interpolators divide a clock frequency intomultiple phases. For example, the interpolator 72 divides a clockfrequency into 128 phases. Interpolation and frequency adjustment isperformed by jumping the phase forward or backward. For example, CLK0 isT/128 before CLK1. CLK3 is 2T/128 after CLK0. CLK0 is 5T/128 beforeCLK6.

[0036] Referring now to FIG. 7, the host 10 and the device 20 may beconnected by a serial ATA medium 180. Referring now to FIG. 8, the host10 can be a disk controller 10-1 and the device 20 can be a disk drive20-1. Still other hosts, devices and connection standards can beemployed.

[0037] Referring now to FIGS. 9-11, several exemplary implementations ofthe PLL 64 are shown. In FIG. 9, the PLL 64 includes a phase detector200 having an input connected to a reference frequency. An output of thephase detector 200 is input to a low pass filter 202, which has anoutput that is connected to a first input of a summer 203. A spreadspectrum control (SSC) signal is input to a second input of the summer203. An output of the summer is input to a voltage controlled oscillator(VCO) 204, which has an output that is fed back to the phase detector200. In FIG. 10, the PLL 64 supports open-loop spread spectrumoperation. The reference frequency is input to a divide by M circuit210. The output of the VCO 204 is fed back through a divide by N circuit214. M and N are modulated to generate a triangular wave.

[0038] In FIG. 11, the PLL 64 supports closed loop spread spectrumoperation. The reference frequency is input to the divide by M circuit210. The output of the VCO 204 is fed back to a first input of aninterpolator 216. A frequency modulation generator 220 outputs a spreadspectrum modulation signal, such as a triangular wave, sine wave, etc.,to an accumulator 220. An output of the accumulator 220 is input to asecond input of the interpolator 216. M and N are modulated to generatea triangular wave. The interpolator 216 provides smoothing. Thereference frequency for the PLL 64 may be generated by a resonator,although other reference frequency generators can be used.

[0039] Those skilled in the art can now appreciate from the foregoingdescription that the broad teachings of the present invention can beimplemented in a variety of forms. Therefore, while this invention hasbeen described in connection with particular examples thereof, the truescope of the invention should not be so limited since othermodifications will become apparent to the skilled practitioner upon astudy of the drawings, the specification and the following claims.

What is claimed is:
 1. A device that communicates with a host,comprising: a transmitter; a receiver; a clock generator that generatesa local clock frequency; a clock recovery circuit that communicates withsaid receiver and that recovers a host clock frequency from datareceived from said host by said receiver; a frequency offset circuitthat communicates with said clock recovery circuit and said clockgenerator and that generates a frequency offset based on said clockfrequency and said recovered host clock frequency; and a frequencycompensator that compensates a frequency of said transmitter using saidfrequency offset.
 2. The device of claim 1 wherein said frequencycompensator includes a low pass filter that communicates with saidfrequency offset circuit.
 3. The device of claim 2 wherein saidfrequency compensator includes an accumulator that communicates withsaid low pass filter and that generates a phase offset.
 4. The device ofclaim 3 wherein said frequency compensator includes an interpolator thatreceives a local phase from said clock generator and said phase offsetfrom said accumulator and wherein said interpolator outputs acompensated clock signal to said transmitter.
 5. The device of claim 1wherein said clock generator includes a phase-locked loop circuit thatincludes: a reference frequency generator; a phase detector thatcommunicates with said reference frequency generator; a low pass filterthat communicates with said phase detector; and a voltage controlledoscillator that communicates with said low pass filter.
 6. The device ofclaim 5 wherein said reference frequency generator includes at least oneof a crystal resonator and a ceramic resonator.
 7. The device of claim 5further comprising a 1/N divider having an input that communicates withsaid voltage controlled oscillator and an output that communicates withsaid phase detector, and a 1/M divider having an input that communicateswith said reference frequency generator and an output that communicateswith said phase detector, wherein N and M are adjusted to create aspread spectrum modulation signal for spread spectrum operation.
 8. Thedevice of claim 7 further comprising an interpolator that communicateswith an output of said voltage controlled oscillator and an input ofsaid 1/N divider.
 9. The device of claim 4 further comprising: a summerhaving a first input that communicates with an output of said lowpassfilter and an output that communicates with an input of saidaccumulator; and a frequency modulation generator that communicates witha second input of said summer and that selectively generates a spreadspectrum modulation signal when spread spectrum operation is enabled anda constant signal when spread spectrum operation is disabled.
 10. Thedevice of claim 1 wherein said host and said device communicate using aserial ATA standard.
 11. The device of claim 1 wherein said host is adisk controller and said device is a disk drive.
 12. A communicationsystem including: a host including a host transmitter, a host receiver,and a host clock generator that generates a host clock frequency; and adevice that communicates with said host using a serial ATA standard andthat includes a device transmitter, a device receiver, a device clockgenerator that generates a local clock frequency, a clock recoverycircuit that recovers said host clock frequency from data received fromsaid host by said device receiver, a frequency offset circuit thatgenerates a frequency offset based on said local clock frequency andsaid recovered host clock frequency, and a frequency compensator thatcompensates a frequency of said device transmitter using said frequencyoffset.
 13. The communication system of claim 12 wherein said frequencycompensator includes a low pass filter that communicates with saidfrequency offset circuit.
 14. The communication system of claim 13wherein said frequency compensator includes an accumulator thatcommunicates with said low pass filter and that generates a phaseoffset.
 15. The communication system of claim 14 wherein said frequencycompensator includes an interpolator that receives a local phase fromsaid device clock generator and said phase offset from said accumulator.16. The communication system of claim 12 wherein said device clockgenerator includes a phase-locked loop circuit that includes: areference frequency generator; a phase detector that communicates withsaid reference frequency generator; a low pass filter that communicateswith said phase detector; and a voltage controlled oscillator thatcommunicates with said low pass filter.
 17. The communication system ofclaim 16 wherein said reference frequency generator includes at leastone of a crystal resonator and a ceramic resonator.
 18. Thecommunication system of claim 16 further comprising a 1/N divider havingan input that communicates with said voltage controlled oscillator andan output that communicates with said phase detector, and a 1/M dividerhaving an input that communicates with said reference frequencygenerator and an output that communicates with said phase detector,wherein N and M are adjusted to create a spread spectrum modulationsignal for spread spectrum operation.
 19. The communication system ofclaim 18 further comprising an interpolator that communicates with anoutput of said voltage controlled oscillator and an input of said 1/Ndivider.
 20. The communication system of claim 15 further comprising: asummer having a first input that communicates with an output of saidlowpass filter and an output that communicates with an input of saidaccumulator; and a frequency modulation generator that communicates witha second input of said summer and that selectively generates a spreadspectrum modulation signal when spread spectrum operation is enabled anda constant when spread spectrum operation is disabled.
 21. Thecommunication system of claim 12 wherein said host is a disk controllerand said device is a disk drive.
 22. A frequency offset compensator fora device that communicates with a host, comprising: a clock datarecovery and frequency offset calculator that generates a frequencyoffset; a frequency modulation generator that generates a spreadspectrum modulation signal when spread spectrum operation is enabled;and a summer that adds said frequency offset and an output of saidfrequency modulation generator to generate a summed frequency offset; aconversion circuit that converts said summed frequency offset to a phaseoffset.
 23. The frequency offset compensator of claim 22 wherein saidfrequency modulation generator outputs a constant when spread spectrumoperation is disabled and wherein said summer adds said frequency offsetand said constant when said spread spectrum operation is disabled. 24.The frequency offset compensator of claim 22 further comprising: adevice transmitter; a device clock that generates a local phase; and aninterpolator that has a first input that receives said local phase, asecond input that receives an output of said summer, and an output thatcommunicates with a transmitter of said device.
 25. A device thatcommunicates with a host, comprising: transmitting means fortransmitting data to said host; receiving means for receiving data fromsaid host; clock generating means for generating a local clockfrequency; clock recovery means for recovering a host clock frequencyfrom data received from said host by said receiving means; frequencyoffset means for generating a frequency offset based on said clockfrequency and said recovered host clock frequency; and frequencycompensating means for compensating a frequency of said transmittingmeans using said frequency offset.
 26. The device of claim 25 whereinsaid frequency compensating means includes filtering means for filteringan output of said frequency offset means.
 27. The device of claim 26wherein said frequency compensating means further includes accumulatingmeans that communicates with said filtering means for generating a phaseoffset.
 28. The device of claim 27 wherein said frequency compensatingmeans further includes interpolating means that receives a local phasefrom said clock generating means and said phase offset from saidaccumulating means for generating a compensated clock signal for saidtransmitting means.
 29. The device of claim 25 wherein said clockgenerating means includes a phase-locked loop circuit that includes:generating means for generating a reference frequency; detecting meansfor detecting a phase of said reference frequency; filtering means forfiltering said phase output by said detecting means; and a voltagecontrolled oscillator that communicates with said filtering means. 30.The device of claim 29 wherein said generating means includes at leastone of a crystal resonator and a ceramic resonator.
 31. The device ofclaim 29 further comprising: first dividing means having an input thatcommunicates with said voltage controlled oscillator and an output thatcommunicates with said detecting means for dividing an output of saidvoltage controlled oscillator by N; and second dividing means having aninput that communicates with said generating means and an output thatcommunicates with said detecting means for dividing said referencefrequency by M, wherein N and M are adjusted to create a spread spectrummodulation signal for spread spectrum operation.
 32. The device of claim31 further comprising: frequency modulation generating means forgenerating a spread spectrum modulation signal; accumulating means thatcommunicates with an output of said frequency modulation generatingmeans for generating a phase from said spread spectrum modulationsignal; and interpolating means for communicating with an output of saidvoltage controlled oscillator and said accumulating means and an inputof said first dividing means.
 33. The device of claim 28 furthercomprising: frequency modulation generating means for selectivelygenerating a spread spectrum modulation signal when spread spectrumoperation is enabled and a constant signal when spread spectrumoperation is disabled; and summing means for summing an output of saidfiltering means and said frequency modulation generating means andhaving an output that communicates with an input of said accumulatingmeans.
 34. The device of claim 25 wherein said host and said devicecommunicate using a serial ATA standard.
 35. The device of claim 25wherein said host is a disk controller and said device is a disk drive.36. A communication system including: a host including host transmittingmeans for transmitting data, host receiving means for receiving data,and host clock generating means for generating a host clock frequency;and a device that communicates with said host using a serial ATAstandard and that includes device transmitting means for transmittingdata, device receiving means for receiving data, device clock generatingmeans for generating a local clock frequency, clock recovery means forrecovering said host clock frequency from data received from said hostby said device receiving means, frequency offset means for generating afrequency offset based on said local clock frequency and said recoveredhost clock frequency, and frequency compensating means for compensatinga frequency of said device transmitting means based on said frequencyoffset.
 37. The communication system of claim 36 wherein said frequencycompensating means includes filtering means for filtering said frequencyoffset.
 38. The communication system of claim 37 wherein said frequencycompensating means further includes accumulating means that communicateswith said filtering means for generating a phase offset.
 39. Thecommunication system of claim 38 wherein said frequency compensatingmeans includes interpolating means for receiving a local phase from saiddevice clock generating means and said phase offset from saidaccumulating means.
 40. The communication system of claim 36 whereinsaid device clock generator includes a phase-locked loop circuit thatincludes: generating means for generating a reference frequency;detecting means for detecting a phase of said reference frequency;filtering means for filtering said phase; and a voltage controlledoscillator that communicates with said filtering means.
 41. Thecommunication system of claim 40 wherein said generating means includesat least one of a crystal resonator and a ceramic resonator.
 42. Thecommunication system of claim 40 further comprising: first dividingmeans having an input that communicates with said voltage controlledoscillator and an output that communicates with said detecting means fordividing an output of said voltage controlled oscillator by N; andsecond dividing means having an input that communicates with saidgenerating means and an output that communicates with said detectingmeans for dividing said reference frequency by M, wherein N and M areadjusted to create a spread spectrum modulation signal for spreadspectrum operation.
 43. The communication system of claim 42 furthercomprising interpolating means for communicating with an output of saidvoltage controlled oscillator and an input of said first dividing means.44. The communication system of claim 39 further comprising: frequencymodulation generating means for selectively generating a spread spectrummodulation signal when spread spectrum operation is enabled and aconstant when spread spectrum operation is disabled; and summing meansfor summing an output of said filtering means and said frequencymodulation generating means and having an output that communicates withan input of said accumulating means.
 45. The communication system ofclaim 36 wherein said host is a disk controller and said device is adisk drive.
 46. A frequency offset compensator for a device thatcommunicates with a host, comprising: offset calculating means forgenerating a frequency offset; frequency modulation generating means forgenerating a spread spectrum modulation signal when spread spectrumoperation is enabled; summing means for generating a summed frequencyoffset by summing said frequency offset and said spread spectrummodulation signal; and conversion means for converting said summedfrequency offset to a phase offset.
 47. The frequency offset compensatorof claim 46 wherein said frequency modulation generating means outputs aconstant when spread spectrum operation is disabled and wherein saidsumming means adds said frequency offset and said constant when saidspread spectrum operation is disabled.
 48. The frequency offsetcompensator of claim 46 further comprising: device transmitting meansfor transmitting data; device clocking means for generating a localphase; and interpolating means for receiving said local phase and saidphase offset and for compensating a clock of said device transmittingmeans.
 49. A method for operating a device that communicates with ahost, comprising: transmitting data to said host; receiving data fromsaid host; generating a local clock frequency; recovering a host clockfrequency from data received from said host; generating a frequencyoffset based on said clock frequency and said recovered host clockfrequency; and compensating a transmitting frequency using saidfrequency offset.
 50. The method of claim 49 further comprising low passfiltering said frequency offset.
 51. The method of claim 50 furthercomprising generating a phase offset from said filtered frequencyoffset.
 52. The method of claim 51 further comprising generating acompensated clock signal for said transmitted data based on a localphase and said phase offset.
 53. The method of claim 49 wherein saidstep of generating said local clock includes using a phase-locked loop.54. The method of claim 53 wherein a reference frequency of saidphase-locked loop is generated by at least one of a crystal resonatorand a ceramic resonator.
 55. A method for providing frequency offsetcompensation for a device that communicates with a host, comprising:generating a frequency offset; generating a spread spectrum modulationsignal when spread spectrum operation is enabled; summing said frequencyoffset and said spread spectrum modulation signal to generate a summedfrequency offset; and converting said summed frequency offset to a phaseoffset.
 56. The method of claim 55 further comprising: generating aconstant signal when spread spectrum operation is disabled; and summingsaid frequency offset and said constant when said spread spectrumoperation is disabled to generate said summed frequency offset.
 57. Themethod of claim 55 further comprising: transmitting data from saiddevice; generating a local phase; and compensating a transmitter clockbased on said local phase and said phase offset.